-
[1] M. Lankamp, T. Bernard, M. Hicks, C. Jesshope, and L. Zhang, Evaluation of a hardware implementation of the SVP concurrency model, in
International Symposium on Computer Architecture (submitted), 2010.
bibtex
@inproceedings{lankamp.10,
author = {Lankamp, Mike and Bernard, Thomas and Hicks, Michael and Jesshope, Chris and Zhang, Li},
Booktitle = {International Symposium on Computer Architecture (submitted)},
Title = {Evaluation of a hardware implementation of the SVP concurrency model},
Year = {2010}
}
-
[2] D. Rolls, C. Joslin, and S. Scholz, Unibench: A Tool for Automated and Collaborative Benchmarking, in
18th IEEE International Conference on Program Comprehension, 2010.
bibtex
@INPROCEEDINGS{ RollJoslScho+ICPC10,
author = {Daniel Rolls and Carl Joslin and Sven-Bodo Scholz},
TITLE = {Unibench: A Tool for Automated and Collaborative Benchmarking},
BOOKTITLE = {18th IEEE International Conference on Program Comprehension},
publisher = {IEEE Computer Society},
year = {2010},
month = {June},
TOPICS = {unibench}
}
-
[3] M. Danvek, L. Kafka, L. Kohout, and J. Sýkora, Instruction Set Extensions for Multi-Threading in LEON3, in
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS2010, 2010, pp. 237-242.
bibtex
@INPROCEEDINGS{DaneKafkKoho+10,
author = {Dan\v{e}k, M. and Kafka, L. and Kohout, L. and S\'{y}kora, J.},
title = {Instruction Set Extensions for Multi-Threading in {LEON3}},
booktitle = {Proceedings of the 13th {IEEE} Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS2010},
pages = {237--242},
editor = {Z. Kot\'{a}sek et al.},
publisher = {IEEE},
ISBN = {978-1-4244-6610-8},
year = {2010}
}
-
[4] S. Herhut, C. Joslin, and S. Scholz, Thread-Local Stacks, a Light-Weight Alternative to Thread-Local Heaps, in
15th Workshop on Compilers for Parallel Computing (CPC’10), Vienna University of Technology, Vienna, Austria, 2010.
bibtex
@INPROCEEDINGS{ HerhJoslSchoCPC10,
author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
TITLE = {{Thread-Local Stacks, a Light-Weight Alternative to Thread-Local Heaps}},
EDITOR = {},
BOOKTITLE = {15th Workshop on Compilers for Parallel Computing (CPC'10), Vienna University of Technology, Vienna, Austria},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2010, PAGES = {},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[5] S. Scholz, S. Herhut, C. Grelck, and F. Penczek, Single Assignment C Tutorial. PPoPP 2010, Bangalore, India, School of Computer Science, University of Hertfordshire, 498, 2010.
bibtex
@TECHREPORT{SchoHerhGrel+10,
author = {Scholz, Sven-Bodo and Herhut, Stephan and Grelck, Clemens and Penczek, Frank},
Institution = {School of Computer Science, University of Hertfordshire},
Number = {498},
Title = {{S}ingle {A}ssignment {C} Tutorial. PPoPP 2010, Bangalore, India},
Year = {2010}
}
-
[6] T. Bernard, C. Grelck, M. Hicks, C. Jesshope, and R. Poss, Resource-Agnostic Many-core Programming through Hardware/Software Co-Design, in
International Conference on Network and Parallel Computing (submitted), 2010.
bibtex
@inproceedings{bernard.10,
author = {Bernard, Thomas and Grelck, Clemens and Hicks, Michael and Jesshope, Chris and Poss, R},
Booktitle = {International Conference on Network and Parallel Computing (submitted)},
Title = {Resource-Agnostic Many-core Programming through Hardware/Software Co-Design},
Year = {2010}
}
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[7] T. Bernard, C. Grelck, and C. Jesshope, On the Compilation of a Language for General Concurrent Target Architectures,
Parallel Processing Letters, vol. 20, 2010.
bibtex
@ARTICLE{a-bernard-ppl-10,
author = {Bernard, Thomas and Grelck, Clemens and Jesshope, Chris},
title = {{O}n the {C}ompilation of a {L}anguage for {G}eneral {C}oncurrent {T}arget {A}rchitectures},
journal = {Parallel Processing Letters},
year = {2010},
volume = {20},
month = {June},
date-modified = {2010-02-02 20:21:40 +0100},
issue = {2},
publisher = {World Scientific}
}
-
[8] K. Stavåker, D. Rolls, J. Guo, and P. Fritzson, Compilation of Modelica Array Computations into Single Assignment C for Efficient Execution on CUDA-enabled GPU, in
3rd International Workshop on Equation-Based Object-Oriented Languages and Tools, Oslo, Norway, 2010.
bibtex
@INPROCEEDINGS{ RollSchoJoslStav+EOOLT10,
author = {Kristian Stavåker and Daniel Rolls and Jing Guo and Peter Fritzson},
TITLE = {Compilation of Modelica Array Computations into Single Assignment C for Efficient Execution on CUDA-enabled GPU},
EDITOR = {},
BOOKTITLE = {3rd International Workshop on Equation-Based Object-Oriented Languages and Tools, Oslo, Norway},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
MONTH = {October},
YEAR = {2010},
TOPICS = {SAC, cuda, Modelica, Openmodelica}
}
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[9] A. Kudryavtsev, D. Rolls, S. Scholz, and A. Shafarenko, Numerical simulations of unsteady shock wave interactions using SAC and Fortran-90, in
10th International Conference on Parallel Computing Technologies (PaCT’09), 2009, pp. 445-456.
bibtex
@INPROCEEDINGS{ RollSchoKudr+PACT09,
author = {Alexei Kudryavtsev and Daniel Rolls and Sven-Bodo Scholz and Alex Shafarenko},
TITLE = {{Numerical simulations of unsteady shock wave interactions using SAC and Fortran-90}},
EDITOR = {},
BOOKTITLE = {10th International Conference on Parallel Computing Technologies (PaCT'09)},
PUBLISHER = {Springer-Verlag, Berlin, Heidelberg, New York},
SERIES = {Lecture Notes in Computer Science},
VOLUME = {5083},
NUMBER = {},
YEAR = 2009, PAGES = {445--456},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[10] C. Grelck, S. Herhut, C. Jesshope, C. Joslin, M. Lankamp, S. Scholz, and A. Shafarenko, Compiling the Functional Data-Parallel Language sac for Microgrids of Self-Adaptive Virtual Processors, in
14th Workshop on Compilers for Parallel Computing (CPC’09), IBM Research Center, Zurich, Switzerland, 2009.
bibtex
@INPROCEEDINGS{ GrelJessJosl+CPC09,
author = {Clemens Grelck and Stephan Herhut and Chris Jesshope and Carl Joslin and Mike Lankamp and Sven-Bodo Scholz and Alex Shafarenko},
TITLE = {{Compiling the Functional Data-Parallel Language sac for Microgrids of Self-Adaptive Virtual Processors}},
EDITOR = {},
BOOKTITLE = {14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2009, PAGES = {},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[11] D. Rolls, S. Herhut, C. Joslin, and S. Scholz, Unibench: The Swiss Army Knife for Collaborative, Automated Benchmarking, Seton Hall University, South Orange, NJ, USA., In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages. SHU-TR-CS-2009-09-1, 2009.
bibtex
@TECHREPORT{RollHerhJosl+IFL09draft,
author = {Daniel Rolls and Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
Institution = {Seton Hall University, South Orange, NJ, USA.},
Number = {SHU-TR-CS-2009-09-1},
Title = {Unibench: The Swiss Army Knife for Collaborative, Automated Benchmarking},
Year = {2009},
Type = {In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages.}
}
-
[12] C. Jesshope, M. Lankamp, and L. Zhang, Evaluating CMPs and their memory architecture, in
Proc. Architecture of Computing Systems, 2009, pp. 246-257.
bibtex
@INPROCEEDINGS{ JessLankZhanARCS09,
author = {C. Jesshope and M. Lankamp and L. Zhang},
TITLE = {{Evaluating CMPs and their memory architecture}},
BOOKTITLE = {Proc. Architecture of Computing Systems},
YEAR = {2009},
EDITOR = {M. Berekovic and C. Muller-Schoer and C. Hochberger and S. Wong},
PAGES = {246-257},
ISBN = {}
}
-
[13] S. Herhut, C. Joslin, S. Scholz, and C. Grelck, Truly Nested Data-Parallelism. Compiling SAC to the Microgrid Architecture, Seton Hall University, South Orange, NJ, USA., In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages. SHU-TR-CS-2009-09-1, 2009.
bibtex
@TECHREPORT{HerhJoslScho+IFL09draft,
author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz and Clemens Grelck},
Institution = {Seton Hall University, South Orange, NJ, USA.},
Number = {SHU-TR-CS-2009-09-1},
Title = {Truly Nested Data-Parallelism. Compiling SAC to the Microgrid Architecture},
Year = {2009},
Type = {In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages.}
}
-
[14] S. Herhut, S. Scholz, and C. Grelck, Controlling Chaos — On Safe Side-Effects in Data-Parallel Operations, in
Annual Symposium on Principles of Programming Languages (POPL), 4th Workshop on Declarative Aspects of Multicore Programming (DAMP’09), Savannah, Georgia, USA, 2009, pp. 59-67.
bibtex
@INPROCEEDINGS{ HerhSchoGrelDAMP09,
author = {Stephan Herhut and Sven-Bodo Scholz and Clemens Grelck},
TITLE = {{Controlling Chaos --- On Safe Side-Effects in Data-Parallel Operations}},
EDITOR = {},
BOOKTITLE = {Annual Symposium on Principles of Programming Languages (POPL), 4th Workshop on Declarative Aspects of Multicore Programming (DAMP'09), Savannah, Georgia, USA},
PUBLISHER = {ACM Press, New York City, New York, USA},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2009, PAGES = {59--67},
ISBN = {978-1-60558-417-1},
DOI = {http://doi.acm.org/10.1145/1481839.1481847},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[15] C. Jesshope, M. Hicks, M. Lankamp, R. Poss, and L. Zhang, Making multi-cores mainstream: from security to scalability, in
Proceedings of International Conference on Parallel Computing (Parco), 2009.
bibtex
@inproceedings{jesshopep.09,
author = {Jesshope, Chris and Hicks, Michael and Lankamp, Mike and Poss, Raphael and Zhang, Li},
Booktitle = {Proceedings of International Conference on Parallel Computing (Parco)},
Title = {Making multi-cores mainstream: from security to scalability},
Year = {2009}
}
-
[16] D. Saougkos, D. Evgenidou, and G. Manis, Specifying Loop Transformations for C2uTC Source to Source Compiler , in
14th Workshop on Compilers for Parallel Computing (CPC’09), IBM Research Center, Zurich, Switzerland, 2009.
bibtex
@INPROCEEDINGS{ SaougkosManis+CPC09,
author = { Dimitris Saougkos and Despina Evgenidou and George Manis },
TITLE = {{Specifying Loop Transformations for C2uTC Source to Source Compiler }},
EDITOR = {},
BOOKTITLE = {14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2009, PAGES = {},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {wp3}
}
-
[17] C. Jesshope, M. Lankamp, and L. Zhang, The implementation of an SVP many-core processor and the evaluation of its memory architecture, in
Special Interest Group on Computer Architecture (SIGARCH), 2009, pp. 38-45.
bibtex
@inproceedings{jessopesig.09,
author = {Jesshope, Chris and Lankamp, Mike and Zhang, Li},
Booktitle = {Special Interest Group on Computer Architecture (SIGARCH)},
Ee = {http://doi.acm.org/10.1145/1577129.1577136},
Pages = {38--45},
Publisher = {ACM},
Series = {LNCS},
Title = {The implementation of an SVP many-core processor and the evaluation of its memory architecture},
Volume = {37},
Year = {2009}
}
-
[18] K. Bousias, L. Guang, C. R. Jesshope, and M. Lankamp, Implementation and Evaluation of a Microthread Architecture,
Journal of Systems Architecture, vol. 55, iss. 3, pp. 149-161, 2009.
bibtex
@ARTICLE{ BousGuanJess+JSA08,
author = {K. Bousias and L. Guang and C.R. Jesshope and M. Lankamp },
TITLE = {{Implementation and Evaluation of a Microthread Architecture}},
JOURNAL = {Journal of Systems Architecture},
YEAR = {2009},
EDITOR = {},
VOLUME = {55},
NUMBER = {3},
PAGES = {149-161},
ISBN = {},
PUBLISHER = {}
}
-
[19] T. D.Vu, L. Zhang, and C. R. Jesshope, The verification of the on-chip COMA cache coherence protocol, in
International Conference on Algebraic Methodology and Software Technology, 2008, pp. 413-429.
bibtex
@INPROCEEDINGS{ VuZhanJessAMAST08,
author = {T. D.Vu and L. Zhang and C. R. Jesshope},
TITLE = {{The verification of the on-chip COMA cache coherence protocol}},
EDITOR = {},
BOOKTITLE = {International Conference on Algebraic Methodology and Software Technology},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2008, PAGES = {413-429},
ISBN = {978-3-540-79979-5},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {}
}
-
[20] S. Herhut, C. Joslin, and S. Scholz, Compiling the Functional Data-Parallel Language SaC for the Self-Adaptive Virtual Processor Architecture, School of Computer Science, University of Hertfordshire, 482, 2008.
bibtex
@TECHREPORT{HerhJoslScho08,
author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
Institution = {School of Computer Science, University of Hertfordshire},
Number = {482},
Title = {Compiling the Functional Data-Parallel Language SaC for the Self-Adaptive Virtual Processor Architecture},
Year = {2008}
}
-
[21] C. Jesshope, Operating systems in silicon and the dynamic management of resources in many-core chips,
Parallel Processing Letters, vol. 18, iss. 2, pp. 257-274, 2008.
bibtex
@ARTICLE{ JessPPL08,
author = {Chris Jesshope},
TITLE = {{Operating systems in silicon and the dynamic management of resources in many-core chips}},
JOURNAL = {Parallel Processing Letters},
YEAR = {2008},
EDITOR = {},
VOLUME = {18},
NUMBER = {2},
PAGES = {257-274},
ISBN = {},
PUBLISHER = {},
ISBN = {}
}
-
[22] C. Jesshope, J. Philippe, and M. van Tol, An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency, in
Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008, pp. 218-228.
bibtex
@INPROCEEDINGS{ JessPhilTolLNCS08,
author = {Chris Jesshope and Jean-Marc Philippe and Michiel van Tol},
TITLE = {{An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency}},
BOOKTITLE = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
YEAR = {2008},
EDITOR = {},
PAGES = {218-228},
ISBN = {978-3-540-70549-9}
}
-
[23] T. Bernard, K. Bousias, L. Guang, C. R. Jesshope, M. Lankamp, M. W. van Tol, and L. Zhang, A general model of concurrency and its implementation as many-core dynamic RISC processors, in
Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008, 2008, pp. 1-9.
bibtex
@INPROCEEDINGS{ BernBousGuan+SAMOS08,
author = {T. Bernard and K. Bousias and L. Guang and C. R. Jesshope and M. Lankamp and M. W. van Tol and L. Zhang},
TITLE = {{A general model of concurrency and its implementation as many-core dynamic RISC processors}},
BOOKTITLE = {Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008},
YEAR = {2008},
EDITOR = {W. Najjar and H. Blume},
PAGES = {1-9},
ISBN = {978-1-4244-1985-2}
}
-
[24] C. Jesshope and A. Shafarenko, Concurrency Engineering, in
Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference, 2008.
bibtex
@INPROCEEDINGS{ JessShafACSAC08,
author = {Chris Jesshope and Alex Shafarenko},
TITLE = {{Concurrency Engineering}},
EDITOR = {},
BOOKTITLE = {Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2008, PAGES = {},
ISBN = {978-1-4244-2683-6},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {}
}
-
[25] C. Jesshope, A model for the design and programming of multi-cores,
Advances in Parallel Computing, vol. High Performance Computing and Grids in Action, iss. 16, pp. 37-55, 2008.
bibtex
@ARTICLE{ JesshopeAPC08,
author = {Chris Jesshope},
TITLE = {{A model for the design and programming of multi-cores}},
JOURNAL = {Advances in Parallel Computing},
YEAR = {2008},
EDITOR = {L. Grandinetti},
VOLUME = {High Performance Computing and Grids in Action},
NUMBER = {16},
PAGES = {37-55},
ISBN = {978-1-58603-839-7},
PUBLISHER = {IOS Press}
}
