-
[1] R. Poss, M. Lankamp, I. M. Uddin, J. Sýkora, and L. Kafka, Heterogeneous integration to simplify many-core architecture simulations, in
Proc. 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012, pp. 17-24.
bibtex
@inproceedings{PosLanUdd+RAPIDO12, Acmid = {2162134},
Author = {Poss, Raphael and Lankamp, Mike and Uddin, M. Irfan and S\'{y}kora, Jaroslav and Kafka, Leo\v{s}},
Booktitle = {Proc. 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
Doi = {10.1145/2162131.2162134},
Isbn = {978-1-4503-1114-4},
Keywords = {hardware multithreading, hardware/software co-design, many-core architecture, simulation, system design, system evaluation, system-on-chip design, vertical approach},
Location = {Paris, France},
Numpages = {8},
Pages = {17--24},
Publisher = {ACM},
Series = {RAPIDO '12},
Title = {Heterogeneous integration to simplify many-core architecture simulations},
Year = {2012}
}
-
[2] I. M. Uddin, C. R. Jesshope, M. W. van Tol, and R. Poss, Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores, in
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, New York, NY, USA, 2012, pp. 1-8.
bibtex
@inproceedings{UddJessvanT+RAPIDO12, Acmid = {2162132},
Address = {New York, NY, USA},
Author = {Uddin, M. Irfan and Jesshope, Chris R. and van Tol, Michiel W. and Poss, Raphael},
Booktitle = {Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
Doi = {10.1145/2162131.2162132},
Isbn = {978-1-4503-1114-4},
Keywords = {automatic annotation of basic blocks with performance, estimation, performance estimation},
Location = {Paris, France},
Numpages = {8},
Pages = {1--8},
Publisher = {ACM},
Series = {RAPIDO '12},
Title = {Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores},
Year = {2012}
}
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[3] R. Poss, C. Grelck, S. Herhut, and S. Scholz, Lazy Reference Counting for the Microgrid, in
Proc. 16th Workshop on on Interaction between Compilers and Computer Architectures (INTERACT’16), 2012.
bibtex
@inproceedings{PosGreHer+INTERACT12,
author = {Raphael Poss and Clemens Grelck and Stephan Herhut and Sven-Bodo Scholz},
Booktitle = {Proc. 16th Workshop on on Interaction between Compilers and Computer Architectures (INTERACT'16)},
Note = {(to appear)},
Publisher = {IEEE},
Title = {Lazy Reference Counting for the {Microgrid}},
Year = {2012}
}
-
[4] R. `. Poss, On the realizability of hardware microthreading—Revisting the general-purpose processor interface: consequences and challenges, PhD Thesis , 2012.
bibtex PDF
@phdthesis{Pos12,
author = {Raphael `kena' Poss},
Isbn = {978-94-6108-320-3},
Publisher = {Gildeprint Drukkerijen},
Url = {http://www.raphael.poss.name/on-the-realizability-of-hardware-microthreading/},
School = {University of Amsterdam},
Title = {On the realizability of hardware microthreading---Revisting the general-purpose processor interface: consequences and challenges},
Year = {2012}
}
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[5] R. Poss, M. Lankamp, Q. Yang, J. Fu, M. W. van Tol, and C. Jesshope, Apple-CORE: Microgrids of SVP cores (invited paper), in
Proc. 15th Euromicro Conference on Digital System Design, Cesme, Izmir, Turkey, 2012.
bibtex
@inproceedings{PosLanYan+DSD12, Address = {Cesme, Izmir, Turkey},
Author = {Raphael Poss and Mike Lankamp and Qiang Yang and Jian Fu and Michiel W. {van Tol} and Chris Jesshope},
Booktitle = {Proc. 15th Euromicro Conference on Digital System Design},
Month = {September},
Note = {(to appear)},
Publisher = {IEEE},
Title = {{Apple-CORE}: {Microgrids} of {SVP} cores (invited paper)},
Year = {2012}
}
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[6] D. M. v e, L. Kafka, L. Kohout, J. Sýkora, and R. Bartosinski,
UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs, Springer, 2012.
bibtex PDF
@book{DanKafKoh12,
author = {M. Dan{\v e}k and L. Kafka and L. Kohout and J. S{\'y}kora and R. Bartosinski},
Isbn = {978-1-4614-2409-3},
Month = {November},
Publisher = {Springer},
Series = {Circuits and Systems},
Title = {{UTLEON3}: Exploring Fine-Grain Multi-Threading in {FPGA}s},
Url = {http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4614-2409-3},
Year = {2012}
}
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[7] R. `. Poss, SL—a “quick and dirty” but working intermediate language for SVP systems, University of Amsterdam, arXiv:1208.4572v1 [cs.PL], , 2012.
bibtex PDF
@techreport{poss.12.sl,
author = {Raphael `kena' Poss},
Institution = {University of Amsterdam},
Number = {arXiv:1208.4572v1 [cs.PL]},
Title = {{SL}---a ``quick and dirty'' but working intermediate language for {SVP} systems},
Url = {http://arxiv.org/abs/1208.4572},
Year = {2012},
Month = {August}
}
-
[8] D. Saougkos, A. Mastoras, and G. Manis, Fine Grained Parallelism in Recursive Function Calls, in
Workshop on Languaged-Based Parallel Programming Models, 2011.
bibtex
@INPROCEEDINGS{ SaougkosManis+LBPPM11,
author = { Dimitris Saougkos and Aristeidis Mastoras and George Manis },
TITLE = {{Fine Grained Parallelism in Recursive Function Calls}},
EDITOR = {},
BOOKTITLE = {Workshop on Languaged-Based Parallel Programming Models},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2011, PAGES = {},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {wp3}
}
-
[9] D. Saougkos and G. Manis, Run–Time Scheduling with the` C2uTC Parallelizing Compiler , in
2nd Workshop on Parallel Programming and Run–Time Management Techniques for Many–Core Architectures, in Workshop Proceedings of the 24th Conference on Computing Systems (ARCS 2011), 2011, pp. 151-157.
bibtex
@INPROCEEDINGS{ SaougkosManis+PARMA11,
author = { Dimitris Saougkos and George Manis },
TITLE = {{Run--Time Scheduling with the` C2uTC Parallelizing Compiler }},
EDITOR = {},
BOOKTITLE = {2nd Workshop on Parallel Programming and Run--Time Management Techniques for Many--Core Architectures, in Workshop Proceedings of the 24th Conference on Computing Systems (ARCS 2011) },
PUBLISHER = {Springer},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2011, PAGES = {151-157},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {wp3}
}
-
[10] S. Herhut, C. Joslin, S. B. Scholz, R. Poss, and C. Grelck, Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences, in
22nd International Symposium on Implementation and Application of Functional Languages (IFL’10), Alphen a/d Rijn, Netherlands, Revised Selected Papers, 2011, pp. 185-202.
bibtex
@INPROCEEDINGS{ HerhJoslScho++IFL10,
author = {S. Herhut and C. Joslin and S.B. Scholz and R. Poss and C. Grelck},
TITLE = {{Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences}},
EDITOR = {J. Haage and M. Moraz\'an },
BOOKTITLE = {22nd International Symposium on Implementation and Application of Functional Languages (IFL'10), Alphen a/d Rijn, Netherlands, Revised Selected Papers},
PUBLISHER = {Springer-Verlag, Berlin, Heidelberg, New York},
SERIES = {Lecture Notes in Computer Science},
VOLUME = {6647},
NUMBER = {},
YEAR = 2011, PAGES = {185--202},
ISBN = {978-3-642-24275-5},
Doi = {10.1007/978-3-642-24276-2_12},
NOTE = {to appear},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[11]
Architecture of Computing Systems – ARCS 2011 – 24th International Conference, Como, Italy, February 24-25, 2011. ProceedingsSpringer, 2011.
bibtex
@proceedings{BerForBri+11, editor = {Mladen Berekovic and William Fornaciari and Uwe Brinkschulte and Cristina Silvano},
title = {Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings},
booktitle = {ARCS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {6566},
year = {2011},
isbn = {978-3-642-19136-7},
ee = {http://dx.doi.org/10.1007/978-3-642-19137-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
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[12] J. Sykora, L. Kafka, M. Danek, and L. Kohout, Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3, in
Proceedings of the 2011 Conference on Architecture of Computing Systems (ARCS 2011), 2011, pp. 110-121.
bibtex
@inproceedings{SykKafDan+ARCS11,
author = {Jaroslav Sykora and Leos Kafka and Martin Danek and Lukas Kohout},
title = {Analysis of Execution Efficiency in the Microthreaded Processor {UTLEON3}},
booktitle = {Proceedings of the 2011 Conference on Architecture of Computing Systems {(ARCS 2011)}},
series = {Lecture Notes in Computer Science},
volume = {6566},
publisher = {Springer},
year = {2011},
pages = {110-121},
ee = {http://dx.doi.org/10.1007/978-3-642-19137-4_10},
crossref = {DBLP:conf/arcs/2011},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
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[13] K. Stavåker, D. Rolls, J. Guo, and P. Fritzson, Compilation of Modelica Array Computations into Single Assignment C for Efficient Execution on CUDA-enabled GPU, in
3rd International Workshop on Equation-Based Object-Oriented Languages and Tools, Oslo, Norway, 2010.
bibtex
@INPROCEEDINGS{ RollSchoJoslStav+EOOLT10,
author = {Kristian Stavåker and Daniel Rolls and Jing Guo and Peter Fritzson},
TITLE = {Compilation of Modelica Array Computations into Single Assignment C for Efficient Execution on CUDA-enabled GPU},
EDITOR = {},
BOOKTITLE = {3rd International Workshop on Equation-Based Object-Oriented Languages and Tools, Oslo, Norway},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
MONTH = {October},
YEAR = {2010},
TOPICS = {SAC, cuda, Modelica, Openmodelica}
}
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[14] T. Bernard, C. Grelck, and C. Jesshope, On the Compilation of a Language for General Concurrent Target Architectures,
Parallel Processing Letters, vol. 20, 2010.
bibtex
@ARTICLE{a-bernard-ppl-10,
author = {Bernard, Thomas and Grelck, Clemens and Jesshope, Chris},
title = {{O}n the {C}ompilation of a {L}anguage for {G}eneral {C}oncurrent {T}arget {A}rchitectures},
journal = {Parallel Processing Letters},
year = {2010},
volume = {20},
month = {June},
date-modified = {2010-02-02 20:21:40 +0100},
issue = {2},
publisher = {World Scientific}
}
-
[15] T. Bernard, C. Grelck, M. Hicks, C. Jesshope, and R. Poss, Resource-agnostic Programming for Many-core Microgrids, in
4th Workshop on Highly Parallel Processing on a Chip, 2010.
bibtex
@inproceedings{BernGrelHickHPPC.10,
author = {Bernard, Thomas and Grelck, Clemens and Hicks, Michael and Jesshope, Chris and Poss, R},
Booktitle = {4th Workshop on Highly Parallel Processing on a Chip},
Title = {Resource-agnostic {P}rogramming for {M}any-core {M}icrogrids},
Year = {2010}
}
-
[16] C. Jesshope, M. Hicks, M. Lankamp, R. Poss, and L. Zhang, Making multi-cores mainstream – from security to scalability, in
Parallel Computing: from Multi-cores and GPUs to Petascale, 2010, pp. 16-31.
bibtex
@InProceedings{JessHicksLankPARCO.09, title = {Making multi-cores mainstream - from security to scalability},
booktitle = {Parallel Computing: from Multi-cores and GPUs to Petascale},
author = {Jesshope, Chris and Hicks, Michael and Lankamp, Mike and Poss, Raphael and Zhang, Li},
publisher = {IOS Press},
pages = {16 - 31},
locaton = {Amsterdam},
isbn = {978-1-60750-529-7},
month = {May},
year = {2010}
}
-
[17] M. A. Hicks, M. W. van Tol, and C. R. Jesshope, Towards Scalable I/O on a Many-core Architecture, in
International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2010, pp. 341-348.
bibtex
@InProceedings{HickvTolJessSAMOS.10, title = {Towards {S}calable {I/O} on a {M}any-core {A}rchitecture},
booktitle = {International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)},
author = {Michael A. Hicks and Michiel W. van Tol and Chris R. Jesshope},
publisher = {IEEE},
month = {July},
pages = {341-348},
isbn = {978-1-4244-7937-5},
year = {2010}
}
-
[18] M. Danek, L. Kafka, L. Kohout, and J. Sykora, Instruction Set Extensions for Multi-Threading in LEON3, in
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS2010, 2010, pp. 237-242.
bibtex
@INPROCEEDINGS{DaneKafkKoho+10,
author = {Danek, M. and Kafka, L. and Kohout, L. and Sykora, J.},
title = {Instruction Set Extensions for Multi-Threading in {LEON3}},
booktitle = {Proceedings of the 13th {IEEE} Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS2010},
pages = {237--242},
editor = {Z. Kotasek et al.},
publisher = {IEEE},
ISBN = {978-1-4244-6610-8},
year = {2010}
}
-
[19] S. Scholz, S. Herhut, C. Grelck, and F. Penczek, Single Assignment C Tutorial. PPoPP 2010, Bangalore, India, School of Computer Science, University of Hertfordshire, 498, , 2010.
bibtex
@TECHREPORT{SchoHerhGrel+10,
author = {Scholz, Sven-Bodo and Herhut, Stephan and Grelck, Clemens and Penczek, Frank},
Institution = {School of Computer Science, University of Hertfordshire},
Number = {498},
Title = {{S}ingle {A}ssignment {C} Tutorial. PPoPP 2010, Bangalore, India},
Year = {2010}
}
-
[20] D. Rolls, C. Joslin, and S. Scholz, Unibench: A Tool for Automated and Collaborative Benchmarking, in
18th IEEE International Conference on Program Comprehension, 2010.
bibtex
@INPROCEEDINGS{ RollJoslScho+ICPC10,
author = {Daniel Rolls and Carl Joslin and Sven-Bodo Scholz},
TITLE = {Unibench: A Tool for Automated and Collaborative Benchmarking},
BOOKTITLE = {18th IEEE International Conference on Program Comprehension},
publisher = {IEEE Computer Society},
year = {2010},
month = {June},
TOPICS = {unibench}
}
-
[21] S. Herhut, C. Joslin, and S. Scholz, Thread-Local Stacks, a Light-Weight Alternative to Thread-Local Heaps, in
15th Workshop on Compilers for Parallel Computing (CPC’10), Vienna University of Technology, Vienna, Austria, 2010.
bibtex
@INPROCEEDINGS{ HerhJoslSchoCPC10,
author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
TITLE = {{Thread-Local Stacks, a Light-Weight Alternative to Thread-Local Heaps}},
EDITOR = {},
BOOKTITLE = {15th Workshop on Compilers for Parallel Computing (CPC'10), Vienna University of Technology, Vienna, Austria},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2010, PAGES = {},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[22] S. Herhut and S. Scholz, Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences, Utrecht University, Utrecht, The Netherlands., In: IFL’10: Draft Proceedings of the 22nd Symposium on Implementation and Application of Functional Languages. , , 2010.
bibtex
@TECHREPORT{HerhSchoIFL10draft,
author = {Stephan Herhut and Sven-Bodo Scholz},
Institution = {Utrecht University, Utrecht, The Netherlands.},
Title = {{Concurrent Non-Deferred Reference Counting on the Microgrid: First Experiences}},
Year = {2010},
Type = {{In: IFL'10: Draft Proceedings of the 22nd Symposium on Implementation and Application of Functional Languages.}}
}
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[23] C. Jesshope, M. Lankamp, and L. Zhang, The implementation of an SVP many-core processor and the evaluation of its memory architecture, in
Special Interest Group on Computer Architecture (SIGARCH), 2009, pp. 38-45.
bibtex
@inproceedings{jessopesig.09,
author = {Jesshope, Chris and Lankamp, Mike and Zhang, Li},
Booktitle = {Special Interest Group on Computer Architecture (SIGARCH)},
Ee = {http://doi.acm.org/10.1145/1577129.1577136},
Pages = {38--45},
Publisher = {ACM},
Series = {LNCS},
Title = {The implementation of an SVP many-core processor and the evaluation of its memory architecture},
Volume = {37},
Year = {2009}
}
-
[24] K. Bousias, L. Guang, C. R. Jesshope, and M. Lankamp, Implementation and Evaluation of a Microthread Architecture,
Journal of Systems Architecture, vol. 55, iss. 3, pp. 149-161, 2009.
bibtex
@ARTICLE{ BousGuanJess+JSA08,
author = {K. Bousias and L. Guang and C.R. Jesshope and M. Lankamp },
TITLE = {{Implementation and Evaluation of a Microthread Architecture}},
JOURNAL = {Journal of Systems Architecture},
YEAR = {2009},
EDITOR = {},
VOLUME = {55},
NUMBER = {3},
PAGES = {149-161},
ISBN = {},
PUBLISHER = {}
}
-
[25] D. Saougkos, D. Evgenidou, and G. Manis, Specifying Loop Transformations for C2uTC Source to Source Compiler , in
14th Workshop on Compilers for Parallel Computing (CPC’09), IBM Research Center, Zurich, Switzerland, 2009.
bibtex
@INPROCEEDINGS{ SaougkosManis+CPC09,
author = { Dimitris Saougkos and Despina Evgenidou and George Manis },
TITLE = {{Specifying Loop Transformations for C2uTC Source to Source Compiler }},
EDITOR = {},
BOOKTITLE = {14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2009, PAGES = {},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {wp3}
}
-
[26] C. Jesshope, M. Lankamp, and L. Zhang, Evaluating CMPs and their memory architecture, in
Proc. Architecture of Computing Systems, 2009, pp. 246-257.
bibtex
@INPROCEEDINGS{ JessLankZhanARCS09,
author = {C. Jesshope and M. Lankamp and L. Zhang},
TITLE = {{Evaluating CMPs and their memory architecture}},
BOOKTITLE = {Proc. Architecture of Computing Systems},
YEAR = {2009},
EDITOR = {M. Berekovic and C. Muller-Schoer and C. Hochberger and S. Wong},
PAGES = {246-257},
ISBN = {}
}
-
[27] S. Herhut, S. Scholz, and C. Grelck, Controlling Chaos — On Safe Side-Effects in Data-Parallel Operations, in
Annual Symposium on Principles of Programming Languages (POPL), 4th Workshop on Declarative Aspects of Multicore Programming (DAMP’09), Savannah, Georgia, USA, 2009, pp. 59-67.
bibtex
@INPROCEEDINGS{ HerhSchoGrelDAMP09,
author = {Stephan Herhut and Sven-Bodo Scholz and Clemens Grelck},
TITLE = {{Controlling Chaos --- On Safe Side-Effects in Data-Parallel Operations}},
EDITOR = {},
BOOKTITLE = {Annual Symposium on Principles of Programming Languages (POPL), 4th Workshop on Declarative Aspects of Multicore Programming (DAMP'09), Savannah, Georgia, USA},
PUBLISHER = {ACM Press, New York City, New York, USA},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2009, PAGES = {59--67},
ISBN = {978-1-60558-417-1},
DOI = {http://doi.acm.org/10.1145/1481839.1481847},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[28] C. Grelck, S. Herhut, C. Jesshope, C. Joslin, M. Lankamp, S. Scholz, and A. Shafarenko, Compiling the Functional Data-Parallel Language sac for Microgrids of Self-Adaptive Virtual Processors, in
14th Workshop on Compilers for Parallel Computing (CPC’09), IBM Research Center, Zurich, Switzerland, 2009.
bibtex
@INPROCEEDINGS{ GrelJessJosl+CPC09,
author = {Clemens Grelck and Stephan Herhut and Chris Jesshope and Carl Joslin and Mike Lankamp and Sven-Bodo Scholz and Alex Shafarenko},
TITLE = {{Compiling the Functional Data-Parallel Language sac for Microgrids of Self-Adaptive Virtual Processors}},
EDITOR = {},
BOOKTITLE = {14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2009, PAGES = {},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[29] A. Kudryavtsev, D. Rolls, S. Scholz, and A. Shafarenko, Numerical simulations of unsteady shock wave interactions using SAC and Fortran-90, in
10th International Conference on Parallel Computing Technologies (PaCT’09), 2009, pp. 445-456.
bibtex
@INPROCEEDINGS{ RollSchoKudr+PACT09,
author = {Alexei Kudryavtsev and Daniel Rolls and Sven-Bodo Scholz and Alex Shafarenko},
TITLE = {{Numerical simulations of unsteady shock wave interactions using SAC and Fortran-90}},
EDITOR = {},
BOOKTITLE = {10th International Conference on Parallel Computing Technologies (PaCT'09)},
PUBLISHER = {Springer-Verlag, Berlin, Heidelberg, New York},
SERIES = {Lecture Notes in Computer Science},
VOLUME = {5083},
NUMBER = {},
YEAR = 2009, PAGES = {445--456},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {SAC}
}
-
[30] D. Rolls, S. Herhut, C. Joslin, and S. Scholz, Unibench: The Swiss Army Knife for Collaborative, Automated Benchmarking, Seton Hall University, South Orange, NJ, USA., In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages. SHU-TR-CS-2009-09-1, , 2009.
bibtex
@TECHREPORT{RollHerhJosl+IFL09draft,
author = {Daniel Rolls and Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
Institution = {Seton Hall University, South Orange, NJ, USA.},
Number = {SHU-TR-CS-2009-09-1},
Title = {Unibench: The Swiss Army Knife for Collaborative, Automated Benchmarking},
Year = {2009},
Type = {In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages.}
}
-
[31] S. Herhut, C. Joslin, S. Scholz, and C. Grelck, Truly Nested Data-Parallelism. Compiling SAC to the Microgrid Architecture, Seton Hall University, South Orange, NJ, USA., In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages. SHU-TR-CS-2009-09-1, , 2009.
bibtex
@TECHREPORT{HerhJoslScho+IFL09draft,
author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz and Clemens Grelck},
Institution = {Seton Hall University, South Orange, NJ, USA.},
Number = {SHU-TR-CS-2009-09-1},
Title = {Truly Nested Data-Parallelism. Compiling SAC to the Microgrid Architecture},
Year = {2009},
Type = {In: IFL ’09: Draft Proceedings of the 21st Symposium on Implementation and Application of Functional Languages.}
}
-
[32] C. Jesshope, Operating systems in silicon and the dynamic management of resources in many-core chips,
Parallel Processing Letters, vol. 18, iss. 2, pp. 257-274, 2008.
bibtex
@ARTICLE{ JessPPL08,
author = {Chris Jesshope},
TITLE = {{Operating systems in silicon and the dynamic management of resources in many-core chips}},
JOURNAL = {Parallel Processing Letters},
YEAR = {2008},
EDITOR = {},
VOLUME = {18},
NUMBER = {2},
PAGES = {257-274},
ISBN = {},
PUBLISHER = {},
ISBN = {}
}
-
[33] C. Jesshope, J. Philippe, and M. van Tol, An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency, in
Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008, pp. 218-228.
bibtex
@INPROCEEDINGS{ JessPhilTolLNCS08,
author = {Chris Jesshope and Jean-Marc Philippe and Michiel van Tol},
TITLE = {{An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency}},
BOOKTITLE = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
YEAR = {2008},
EDITOR = {},
PAGES = {218-228},
ISBN = {978-3-540-70549-9}
}
-
[34] T. Bernard, K. Bousias, L. Guang, C. R. Jesshope, M. Lankamp, M. W. van Tol, and L. Zhang, A general model of concurrency and its implementation as many-core dynamic RISC processors, in
Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008, 2008, pp. 1-9.
bibtex
@INPROCEEDINGS{ BernBousGuan+SAMOS08,
author = {T. Bernard and K. Bousias and L. Guang and C. R. Jesshope and M. Lankamp and M. W. van Tol and L. Zhang},
TITLE = {{A general model of concurrency and its implementation as many-core dynamic RISC processors}},
BOOKTITLE = {Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008},
YEAR = {2008},
EDITOR = {W. Najjar and H. Blume},
PAGES = {1-9},
ISBN = {978-1-4244-1985-2}
}
-
[35] C. Jesshope, A model for the design and programming of multi-cores,
Advances in Parallel Computing, vol. High Performance Computing and Grids in Action, iss. 16, pp. 37-55, 2008.
bibtex
@ARTICLE{ JesshopeAPC08,
author = {Chris Jesshope},
TITLE = {{A model for the design and programming of multi-cores}},
JOURNAL = {Advances in Parallel Computing},
YEAR = {2008},
EDITOR = {L. Grandinetti},
VOLUME = {High Performance Computing and Grids in Action},
NUMBER = {16},
PAGES = {37-55},
ISBN = {978-1-58603-839-7},
PUBLISHER = {IOS Press}
}
-
[36] T. D.Vu, L. Zhang, and C. R. Jesshope, The verification of the on-chip COMA cache coherence protocol, in
International Conference on Algebraic Methodology and Software Technology, 2008, pp. 413-429.
bibtex
@INPROCEEDINGS{ VuZhanJessAMAST08,
author = {T. D.Vu and L. Zhang and C. R. Jesshope},
TITLE = {{The verification of the on-chip COMA cache coherence protocol}},
EDITOR = {},
BOOKTITLE = {International Conference on Algebraic Methodology and Software Technology},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2008, PAGES = {413-429},
ISBN = {978-3-540-79979-5},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {}
}
-
[37] C. Jesshope and A. Shafarenko, Concurrency Engineering, in
Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference, 2008.
bibtex
@INPROCEEDINGS{ JessShafACSAC08,
author = {Chris Jesshope and Alex Shafarenko},
TITLE = {{Concurrency Engineering}},
EDITOR = {},
BOOKTITLE = {Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference},
PUBLISHER = {},
SERIES = {},
VOLUME = {},
NUMBER = {},
YEAR = 2008, PAGES = {},
ISBN = {978-1-4244-2683-6},
NOTE = {},
CONTENTS = {},
sourceURL = {},
TOPICS = {}
}
-
[38] S. Herhut, C. Joslin, and S. Scholz, Compiling the Functional Data-Parallel Language SaC for the Self-Adaptive Virtual Processor Architecture, School of Computer Science, University of Hertfordshire, 482, , 2008.
bibtex
@TECHREPORT{HerhJoslScho08,
author = {Stephan Herhut and Carl Joslin and Sven-Bodo Scholz},
Institution = {School of Computer Science, University of Hertfordshire},
Number = {482},
Title = {Compiling the Functional Data-Parallel Language SaC for the Self-Adaptive Virtual Processor Architecture},
Year = {2008}
}
